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https://github.com/coolsnowwolf/lede.git
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103 lines
3.8 KiB
Diff
103 lines
3.8 KiB
Diff
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From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001
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From: Kewei Xu <kewei.xu@mediatek.com>
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Date: Sun, 10 Oct 2021 15:05:13 +0800
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Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout
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occurs
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When a timeout error occurs in i2c transter, it is usually related
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to the i2c/dma IP hardware configuration. Therefore, the purpose of
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this patch is to dump the key register values of i2c/dma when a
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timeout occurs in i2c for debugging.
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Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
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Reviewed-by: Qii Wang <qii.wang@mediatek.com>
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Signed-off-by: Wolfram Sang <wsa@kernel.org>
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---
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drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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--- a/drivers/i2c/busses/i2c-mt65xx.c
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+++ b/drivers/i2c/busses/i2c-mt65xx.c
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@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET {
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OFFSET_HS,
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OFFSET_SOFTRESET,
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OFFSET_DCM_EN,
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+ OFFSET_MULTI_DMA,
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OFFSET_PATH_DIR,
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OFFSET_DEBUGSTAT,
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OFFSET_DEBUGCTRL,
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@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = {
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[OFFSET_TRANSFER_LEN_AUX] = 0x44,
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[OFFSET_CLOCK_DIV] = 0x48,
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[OFFSET_SOFTRESET] = 0x50,
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+ [OFFSET_MULTI_DMA] = 0x8c,
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[OFFSET_SCL_MIS_COMP_POINT] = 0x90,
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[OFFSET_DEBUGSTAT] = 0xe4,
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[OFFSET_DEBUGCTRL] = 0xe8,
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@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_
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return 0;
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}
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+static void i2c_dump_register(struct mtk_i2c *i2c)
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+{
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+ dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
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+ mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
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+ dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
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+ mtk_i2c_readw(i2c, OFFSET_CONTROL));
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+ dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
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+ mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
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+ dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
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+ mtk_i2c_readw(i2c, OFFSET_TIMING));
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+ dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_START),
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+ mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
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+ dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_HS),
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+ mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
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+ dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_DCM_EN),
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+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
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+ dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
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+ mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
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+ dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
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+ mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
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+ if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
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+ dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
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+ mtk_i2c_readw(i2c, OFFSET_LTIMING),
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+ mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
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+ }
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+ dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
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+ readl(i2c->pdmabase + OFFSET_INT_FLAG),
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+ readl(i2c->pdmabase + OFFSET_INT_EN));
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+ dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
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+ readl(i2c->pdmabase + OFFSET_EN),
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+ readl(i2c->pdmabase + OFFSET_CON));
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+ dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
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+ readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
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+ readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
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+ dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
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+ readl(i2c->pdmabase + OFFSET_TX_LEN),
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+ readl(i2c->pdmabase + OFFSET_RX_LEN));
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+ dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
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+ readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
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+ readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
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+}
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+
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static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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int num, int left_num)
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{
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@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt
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if (ret == 0) {
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dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
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+ i2c_dump_register(i2c);
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mtk_i2c_init_hw(i2c);
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return -ETIMEDOUT;
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}
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