lede/target/linux/generic/backport-6.12/731-v6.15-net-phy-mediatek-Add-token-ring-set-bit-operation-su.patch

From c7e2fb3421ef5ebbb4c91f44bd735ab10edd755a Mon Sep 17 00:00:00 2001
From: Sky Huang <skylake.huang@mediatek.com>
Date: Thu, 13 Feb 2025 16:05:51 +0800
Subject: [PATCH 12/20] net: phy: mediatek: Add token ring set bit operation
 support

Previously in mtk-ge-soc.c, we set some register bits via token
ring, which were implemented in three __phy_write().
Now we can do the same thing via __mtk_tr_set_bits() helper.

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-4-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
 drivers/net/phy/mediatek/mtk-ge-soc.c  | 10 ++++++----
 drivers/net/phy/mediatek/mtk-phy-lib.c |  7 +++++++
 drivers/net/phy/mediatek/mtk.h         |  2 ++
 3 files changed, 15 insertions(+), 4 deletions(-)

--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -62,6 +62,10 @@
 /* MasDSPreadyTime */
 #define MASTER_DSP_READY_TIME_MASK		GENMASK(14, 7)
 
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
+/* EnabRandUpdTrig */
+#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER	BIT(8)
+
 /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
 /* ResetSyncOffset */
 #define RESET_SYNC_OFFSET_MASK			GENMASK(11, 8)
@@ -789,10 +793,8 @@ static void mt798x_phy_common_finetune(s
 			FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
 			FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
 
-	/* EnabRandUpdTrig = 1 */
-	__phy_write(phydev, 0x11, 0x2f00);
-	__phy_write(phydev, 0x12, 0xe);
-	__phy_write(phydev, 0x10, 0x8fb0);
+	__mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
+			  ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
 
 	__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
 			NORMAL_MSE_LO_THRESH_MASK,
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -69,6 +69,13 @@ void mtk_tr_modify(struct phy_device *ph
 }
 EXPORT_SYMBOL_GPL(mtk_tr_modify);
 
+void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+		       u8 data_addr, u32 set)
+{
+	__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
+}
+EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
+
 int mtk_phy_read_page(struct phy_device *phydev)
 {
 	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -72,6 +72,8 @@ void __mtk_tr_modify(struct phy_device *
 		     u8 data_addr, u32 mask, u32 set);
 void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 		   u8 data_addr, u32 mask, u32 set);
+void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+		       u8 data_addr, u32 set);
 
 int mtk_phy_read_page(struct phy_device *phydev);
 int mtk_phy_write_page(struct phy_device *phydev, int page);