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rockchip: add support for Ariaboard Photonicat 2 (RK3576)
This commit is contained in:
coolsnowwolf
parent
eef271a975
commit
3d1de3a405
@ -7,8 +7,8 @@ BOARDNAME:=Rockchip
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FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
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SUBTARGETS:=armv8
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KERNEL_PATCHVER:=6.6
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KERNEL_TESTING_PATCHVER:=6.12
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KERNEL_PATCHVER:=6.12
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KERNEL_TESTING_PATCHVER:=6.6
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define Target/Description
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Build firmware image for Rockchip SoC devices.
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@ -10,6 +10,7 @@ rockchip_setup_interfaces()
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case "$board" in
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advantech,rsb4810|\
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ariaboard,photonicat|\
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ariaboard,photonicat2|\
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dilusense,dlfr100|\
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ezpro,mrkaio-m68s|\
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ezpro,mrkaio-m68s-plus|\
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@ -102,6 +103,7 @@ rockchip_setup_macs()
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armsom,sige*|\
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advantech,rsb4810|\
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ariaboard,photonicat|\
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ariaboard,photonicat2|\
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codinge,xiaobao-nas-v1|\
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dilusense,dlfr100|\
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ezpro,mrkaio-m68s|\
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@ -0,0 +1,987 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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thermal_zones: thermal-zones {
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/* sensor near the center of the SoC */
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package_thermal: package-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 0>;
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trips {
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package_crit: package-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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/* sensor for cluster1 (big Cortex-A72 cores) */
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bigcore_thermal: bigcore-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 1>;
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trips {
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bigcore_alert: bigcore-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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bigcore_crit: bigcore-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&bigcore_alert>;
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cooling-device =
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<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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/* sensor for cluster0 (little Cortex-A53 cores) */
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littlecore_thermal: littlecore-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 2>;
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trips {
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littlecore_alert: littlecore-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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littlecore_crit: littlecore-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&littlecore_alert>;
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cooling-device =
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<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu_thermal: gpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 3>;
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trips {
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gpu_alert: gpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_crit: gpu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&gpu_alert>;
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cooling-device =
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<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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npu_thermal: npu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 4>;
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trips {
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npu_crit: npu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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ddr_thermal: ddr-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&tsadc 5>;
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trips {
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ddr_crit: ddr-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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soc {
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vo1_grf: syscon@26036000 {
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compatible = "rockchip,rk3576-vo-grf", "syscon";
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reg = <0x0 0x26036000 0x0 0x100>;
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clocks = <&cru PCLK_VO1_ROOT>;
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};
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hdptxphy_grf: syscon@26032000 {
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compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
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reg = <0x0 0x26032000 0x0 0x100>;
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clocks = <&cru PCLK_PMUPHY_ROOT>;
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};
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usbdp_phy: phy@2b010000 {
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compatible = "rockchip,rk3576-usbdp-phy";
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reg = <0x0 0x2b010000 0x0 0x10000>;
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#phy-cells = <1>;
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clocks = <&cru CLK_PHY_REF_SRC >,
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<&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
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<&cru PCLK_USBDPPHY>,
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<&u2phy0>;
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clock-names = "refclk", "immortal", "pclk", "utmi";
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resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
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<&cru SRST_USBDP_COMBO_PHY_CMN>,
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<&cru SRST_USBDP_COMBO_PHY_LANE>,
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<&cru SRST_USBDP_COMBO_PHY_PCS>,
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<&cru SRST_P_USBDPPHY>;
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reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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rockchip,u2phy-grf = <&usb2phy_grf>;
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rockchip,usb-grf = <&usb_grf>;
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rockchip,usbdpphy-grf = <&usbdpphy_grf>;
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rockchip,vo-grf = <&vo1_grf>;
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status = "disabled";
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};
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usb2phy_grf: syscon@2602e000 {
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compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
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reg = <0x0 0x2602e000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru PCLK_PMUPHY_ROOT>;
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u2phy0: usb2-phy@0 {
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compatible = "rockchip,rk3576-usb2phy";
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reg = <0x0 0x10>;
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resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
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reset-names = "phy", "apb";
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clocks = <&cru CLK_PHY_REF_SRC>,
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<&cru ACLK_MMU2>,
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<&cru ACLK_SLV_MMU2>;
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clock-names = "phyclk", "aclk", "aclk_slv";
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clock-output-names = "usb480m_phy0";
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#clock-cells = <0>;
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status = "disabled";
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u2phy0_otg: otg-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id", "linestate";
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status = "disabled";
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};
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};
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u2phy1: usb2-phy@2000 {
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compatible = "rockchip,rk3576-usb2phy";
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reg = <0x2000 0x10>;
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resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
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reset-names = "phy", "apb";
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clocks = <&cru CLK_PHY_REF_SRC>,
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<&cru ACLK_MMU1>,
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<&cru ACLK_SLV_MMU1>;
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clock-names = "phyclk", "aclk", "aclk_slv";
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clock-output-names = "usb480m_phy1";
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#clock-cells = <0>;
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status = "disabled";
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u2phy1_otg: otg-port {
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#phy-cells = <0>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id", "linestate";
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status = "disabled";
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};
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};
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};
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usb_drd0_dwc3: usb@23000000 {
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compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
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reg = <0x0 0x23000000 0x0 0x400000>;
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clocks = <&cru CLK_REF_USB3OTG0>,
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<&cru CLK_SUSPEND_USB3OTG0>,
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<&cru ACLK_USB3OTG0>;
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clock-names = "ref", "suspend", "bus_clk";
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interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&power RK3576_PD_USB>;
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resets = <&cru SRST_A_USB3OTG0>;
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reset-names = "usb3-otg";
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dr_mode = "otg";
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phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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snps,parkmode-disable-hs-quirk;
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snps,parkmode-disable-ss-quirk;
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status = "disabled";
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};
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usb_drd1_dwc3: usb@23400000 {
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compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
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reg = <0x0 0x23400000 0x0 0x400000>;
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clocks = <&cru CLK_REF_USB3OTG1>,
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<&cru CLK_SUSPEND_USB3OTG1>,
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<&cru ACLK_USB3OTG1>;
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clock-names = "ref", "suspend", "bus_clk";
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interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&power RK3576_PD_PHP>;
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resets = <&cru SRST_A_USB3OTG1>;
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reset-names = "usb3-otg";
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dr_mode = "otg";
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phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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snps,dis_rxdet_inp3_quirk;
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snps,parkmode-disable-hs-quirk;
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snps,parkmode-disable-ss-quirk;
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dma-coherent;
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status = "disabled";
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};
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combphy0_ps: phy@2b050000 {
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compatible = "rockchip,rk3576-naneng-combphy";
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reg = <0x0 0x2b050000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&cru CLK_REF_PCIE0_PHY>,
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<&cru PCLK_PCIE2_COMBOPHY0>,
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<&cru PCLK_PCIE0>;
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clock-names = "ref", "apb", "pipe";
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assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PCIE0_PIPE_PHY>,
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<&cru SRST_P_PCIE2_COMBOPHY0>;
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reset-names = "phy", "apb";
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rockchip,pipe-grf = <&php_grf>;
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rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
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status = "disabled";
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};
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combphy1_psu: phy@2b060000 {
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compatible = "rockchip,rk3576-naneng-combphy";
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reg = <0x0 0x2b060000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&cru CLK_REF_PCIE1_PHY>,
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<&cru PCLK_PCIE2_COMBOPHY1>,
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<&cru PCLK_PCIE1>;
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clock-names = "ref", "apb", "pipe";
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assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PCIE1_PIPE_PHY>,
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<&cru SRST_P_PCIE2_COMBOPHY1>;
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reset-names = "phy", "apb";
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rockchip,pipe-grf = <&php_grf>;
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rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
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status = "disabled";
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};
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pcie0: pcie@2a200000 {
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compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
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<&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
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<&cru CLK_PCIE0_AUX>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux";
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device_type = "pci";
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interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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linux,pci-domain = <0>;
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num-ib-windows = <8>;
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num-viewport = <8>;
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num-ob-windows = <2>;
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max-link-speed = <2>;
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num-lanes = <1>;
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phys = <&combphy0_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3576_PD_PHP>;
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ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
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0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
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0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
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reg = <0x0 0x22000000 0x0 0x00400000>,
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<0x0 0x2a200000 0x0 0x00010000>,
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<0x0 0x20000000 0x0 0x00100000>;
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reg-names = "dbi", "apb", "config";
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resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
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reset-names = "pwr", "pipe";
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status = "disabled";
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pcie0_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
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};
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};
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pcie1: pcie@2a210000 {
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compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
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<&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
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<&cru CLK_PCIE1_AUX>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk",
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"aux";
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device_type = "pci";
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||||
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
|
||||
<0 0 0 2 &pcie1_intc 1>,
|
||||
<0 0 0 3 &pcie1_intc 2>,
|
||||
<0 0 0 4 &pcie1_intc 3>;
|
||||
linux,pci-domain = <1>;
|
||||
num-ib-windows = <8>;
|
||||
num-viewport = <8>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <2>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy1_psu PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3576_PD_SUBPHP>;
|
||||
ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
|
||||
0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
|
||||
0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
|
||||
reg = <0x0 0x22400000 0x0 0x00400000>,
|
||||
<0x0 0x2a210000 0x0 0x00010000>,
|
||||
<0x0 0x21000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
vop: vop@27d00000 {
|
||||
compatible = "rockchip,rk3576-vop";
|
||||
reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
|
||||
reg-names = "vop", "gamma-lut";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "sys",
|
||||
"vp0",
|
||||
"vp1",
|
||||
"vp2";
|
||||
clocks = <&cru ACLK_VOP>,
|
||||
<&cru HCLK_VOP>,
|
||||
<&cru DCLK_VP0>,
|
||||
<&cru DCLK_VP1>,
|
||||
<&cru DCLK_VP2>,
|
||||
<&hdptxphy>;
|
||||
clock-names = "aclk",
|
||||
"hclk",
|
||||
"dclk_vp0",
|
||||
"dclk_vp1",
|
||||
"dclk_vp2",
|
||||
"pll_hdmiphy0";
|
||||
iommus = <&vop_mmu>;
|
||||
power-domains = <&power RK3576_PD_VOP>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,pmu = <&pmu>;
|
||||
status = "disabled";
|
||||
|
||||
vop_out: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vp0: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
vp1: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
vp2: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vop_mmu: iommu@27d07e00 {
|
||||
compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
|
||||
reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "vop_mmu";
|
||||
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
clock-names = "aclk", "iface";
|
||||
#iommu-cells = <0>;
|
||||
power-domains = <&power RK3576_PD_VOP>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi: hdmi@27da0000 {
|
||||
compatible = "rockchip,rk3576-dw-hdmi-qp";
|
||||
reg = <0x0 0x27da0000 0x0 0x20000>;
|
||||
clocks = <&cru PCLK_HDMITX0>,
|
||||
<&cru CLK_HDMITX0_EARC>,
|
||||
<&cru CLK_HDMITX0_REF>,
|
||||
<&cru MCLK_SAI6_8CH>,
|
||||
<&cru CLK_HDMITXHDP>,
|
||||
<&cru HCLK_VO0_ROOT>;
|
||||
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
|
||||
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
||||
phys = <&hdptxphy>;
|
||||
phy-names = "hdmi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
|
||||
power-domains = <&power RK3576_PD_VO0>;
|
||||
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
|
||||
reset-names = "ref", "hdp";
|
||||
rockchip,grf = <&ioc_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hdmi_in: port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
hdmi_out: port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdptxphy: hdmiphy@2b000000 {
|
||||
compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
|
||||
reg = <0x0 0x2b000000 0x0 0x2000>;
|
||||
clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
|
||||
clock-names = "ref", "apb";
|
||||
#clock-cells = <0>;
|
||||
resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
|
||||
<&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
|
||||
reset-names = "apb", "init", "cmn", "lane";
|
||||
rockchip,grf = <&hdptxphy_grf>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsadc: tsadc@2ae70000 {
|
||||
compatible = "rockchip,rk3576-tsadc";
|
||||
reg = <0x0 0x2ae70000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
assigned-clocks = <&cru CLK_TSADC>;
|
||||
assigned-clock-rates = <2000000>;
|
||||
resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
|
||||
reset-names = "tsadc-apb", "tsadc";
|
||||
#thermal-sensor-cells = <1>;
|
||||
rockchip,hw-tshut-temp = <120000>;
|
||||
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tsadc@0 {
|
||||
reg = <0>;
|
||||
nvmem-cells = <&soc_tsadc_trim_l>, <&soc_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@1 {
|
||||
reg = <1>;
|
||||
nvmem-cells = <&bigcore_tsadc_trim_l>, <&bigcore_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@2 {
|
||||
reg = <2>;
|
||||
nvmem-cells = <&litcore_tsadc_trim_l>, <&litcore_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@3 {
|
||||
reg = <3>;
|
||||
nvmem-cells = <&ddr_tsadc_trim_l>, <&ddr_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@4 {
|
||||
reg = <4>;
|
||||
nvmem-cells = <&npu_tsadc_trim_l>, <&npu_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
tsadc@5 {
|
||||
reg = <5>;
|
||||
nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
};
|
||||
};
|
||||
|
||||
pwm0_2ch_0: pwm@27330000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x27330000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0m0_ch0>;
|
||||
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
||||
clock-names = "pwm", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0_2ch_1: pwm@27331000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x27331000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#pwm-cells = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0m0_ch1>;
|
||||
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
||||
clock-names = "pwm", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_0: pwm@2add0000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add0000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch0>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_1: pwm@2add1000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add1000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch1>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_2: pwm@2add2000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add2000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_3: pwm@2add3000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add3000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch3>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_4: pwm@2add4000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add4000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch4>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1_6ch_5: pwm@2add5000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2add5000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, <&cru CLK_OSC_PWM1>;
|
||||
clock-names = "pwm", "pclk", "osc";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1m0_ch5>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_0: pwm@2ade0000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade0000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch0>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_1: pwm@2ade1000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade1000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch1>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_2: pwm@2ade2000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade2000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch2>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_3: pwm@2ade3000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade3000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch3>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_4: pwm@2ade4000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade4000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch4>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_5: pwm@2ade5000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade5000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch5>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_6: pwm@2ade6000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade6000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch6>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2_8ch_7: pwm@2ade7000 {
|
||||
compatible = "rockchip,rk3576-pwm";
|
||||
reg = <0x0 0x2ade7000 0x0 0x1000>;
|
||||
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
clock-names = "pwm", "pclk";
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2m0_ch7>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai0: sai@2a600000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a600000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac0 0>, <&dmac0 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai0m0_lrck
|
||||
&sai0m0_sclk
|
||||
&sai0m0_sdi0
|
||||
&sai0m0_sdi1
|
||||
&sai0m0_sdi2
|
||||
&sai0m0_sdi3
|
||||
&sai0m0_sdo0
|
||||
&sai0m0_sdo1
|
||||
&sai0m0_sdo2
|
||||
&sai0m0_sdo3>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai1: sai@2a610000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a610000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac0 2>, <&dmac0 3>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai1m0_lrck
|
||||
&sai1m0_sclk
|
||||
&sai1m0_sdi0
|
||||
&sai1m0_sdo0
|
||||
&sai1m0_sdo1
|
||||
&sai1m0_sdo2
|
||||
&sai1m0_sdo3>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai2: sai@2a620000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a620000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac1 0>, <&dmac1 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai2m0_lrck
|
||||
&sai2m0_sclk
|
||||
&sai2m0_sdi
|
||||
&sai2m0_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai3: sai@2a630000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a630000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac1 2>, <&dmac1 3>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai3m0_lrck
|
||||
&sai3m0_sclk
|
||||
&sai3m0_sdi
|
||||
&sai3m0_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai4: sai@2a640000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x2a640000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac2 0>, <&dmac2 1>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_AUDIO>;
|
||||
resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
|
||||
reset-names = "m", "h";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sai4m0_lrck
|
||||
&sai4m0_sclk
|
||||
&sai4m0_sdi
|
||||
&sai4m0_sdo>;
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai5: sai@27d40000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x27d40000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac2 3>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3576_PD_VO0>;
|
||||
resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
|
||||
reset-names = "m", "h";
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai6: sai@27d50000 {
|
||||
compatible = "rockchip,rk3576-sai";
|
||||
reg = <0x0 0x27d50000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
|
||||
clock-names = "mclk", "hclk";
|
||||
dmas = <&dmac2 4>, <&dmac2 5>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&power RK3576_PD_VO0>;
|
||||
resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
|
||||
reset-names = "m", "h";
|
||||
#sound-dai-cells = <0>;
|
||||
sound-name-prefix = "SAI6";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&otp {
|
||||
bigcore_tsadc_trim_l: bigcore-tsadc-trim-l@24 {
|
||||
reg = <0x24 0x1>;
|
||||
};
|
||||
bigcore_tsadc_trim_h: bigcore-tsadc-trim-h@25 {
|
||||
reg = <0x25 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
litcore_tsadc_trim_l: litcore-tsadc-trim-l@26 {
|
||||
reg = <0x26 0x1>;
|
||||
};
|
||||
litcore_tsadc_trim_h: litcore-tsadc-trim-h@27 {
|
||||
reg = <0x27 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
ddr_tsadc_trim_l: ddr-tsadc-trim-l@28 {
|
||||
reg = <0x28 0x1>;
|
||||
};
|
||||
ddr_tsadc_trim_h: ddr-tsadc-trim-h@29 {
|
||||
reg = <0x29 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
npu_tsadc_trim_l: npu-tsadc-trim-l@2a {
|
||||
reg = <0x2a 0x1>;
|
||||
};
|
||||
npu_tsadc_trim_h: npu-tsadc-trim-h@2b {
|
||||
reg = <0x2b 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
gpu_tsadc_trim_l: gpu-tsadc-trim-l@2c {
|
||||
reg = <0x2c 0x1>;
|
||||
};
|
||||
gpu_tsadc_trim_h: gpu-tsadc-trim-h@2d {
|
||||
reg = <0x2d 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
soc_tsadc_trim_l: soc-tsadc-trim-l@64 {
|
||||
reg = <0x64 0x1>;
|
||||
};
|
||||
soc_tsadc_trim_h: soc-tsadc-trim-h@65 {
|
||||
reg = <0x65 0x1>;
|
||||
bits = <0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -22,6 +22,16 @@ define Device/ariaboard_photonicat
|
||||
endef
|
||||
TARGET_DEVICES += ariaboard_photonicat
|
||||
|
||||
define Device/ariaboard_photonicat2
|
||||
DEVICE_VENDOR := Ariaboard
|
||||
DEVICE_MODEL := Photonicat2
|
||||
SOC := rk3576
|
||||
DEVICE_DTS := rockchip/rk3576-photonicat2
|
||||
UBOOT_DEVICE_NAME := evb-rk3576
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script rk3576 | pine64-img | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += ariaboard_photonicat2
|
||||
|
||||
define Device/armsom_sige1
|
||||
DEVICE_VENDOR := ArmSoM
|
||||
DEVICE_MODEL := Sige1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user