From ee5af82a6f88fd28849ea6d98cf43fbe9cbbbb19 Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Thu, 11 Aug 2022 15:15:28 +0800 Subject: [PATCH] pinctrl: rockchip: add rk3528 support Signed-off-by: Steven Liu Change-Id: I2c1d32907168caf8a8afee6d1f742795b3d13536 --- drivers/pinctrl/pinctrl-rockchip.c | 196 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 196 insertions(+), 1 deletion(-) --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2036,6 +2036,150 @@ static int rk3568_calc_pull_reg_and_bit( return 0; } +#define RK3528_DRV_BITS_PER_PIN 8 +#define RK3528_DRV_PINS_PER_REG 2 +#define RK3528_DRV_GPIO0_OFFSET 0x100 +#define RK3528_DRV_GPIO1_OFFSET 0x20120 +#define RK3528_DRV_GPIO2_OFFSET 0x30160 +#define RK3528_DRV_GPIO3_OFFSET 0x20190 +#define RK3528_DRV_GPIO4_OFFSET 0x101C0 + +static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3528_DRV_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3528_DRV_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3528_DRV_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3528_DRV_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3528_DRV_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_DRV_PINS_PER_REG; + *bit *= RK3528_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3528_PULL_BITS_PER_PIN 2 +#define RK3528_PULL_PINS_PER_REG 8 +#define RK3528_PULL_GPIO0_OFFSET 0x200 +#define RK3528_PULL_GPIO1_OFFSET 0x20210 +#define RK3528_PULL_GPIO2_OFFSET 0x30220 +#define RK3528_PULL_GPIO3_OFFSET 0x20230 +#define RK3528_PULL_GPIO4_OFFSET 0x10240 + +static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3528_PULL_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3528_PULL_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3528_PULL_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3528_PULL_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3528_PULL_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_PULL_PINS_PER_REG; + *bit *= RK3528_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3528_SMT_BITS_PER_PIN 1 +#define RK3528_SMT_PINS_PER_REG 8 +#define RK3528_SMT_GPIO0_OFFSET 0x400 +#define RK3528_SMT_GPIO1_OFFSET 0x20410 +#define RK3528_SMT_GPIO2_OFFSET 0x30420 +#define RK3528_SMT_GPIO3_OFFSET 0x20430 +#define RK3528_SMT_GPIO4_OFFSET 0x10440 + +static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + switch (bank->bank_num) { + case 0: + *reg = RK3528_SMT_GPIO0_OFFSET; + break; + + case 1: + *reg = RK3528_SMT_GPIO1_OFFSET; + break; + + case 2: + *reg = RK3528_SMT_GPIO2_OFFSET; + break; + + case 3: + *reg = RK3528_SMT_GPIO3_OFFSET; + break; + + case 4: + *reg = RK3528_SMT_GPIO4_OFFSET; + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); + *bit = pin_num % RK3528_SMT_PINS_PER_REG; + *bit *= RK3528_SMT_BITS_PER_PIN; + return 0; +} + #define RK3568_DRV_PMU_OFFSET 0x70 #define RK3568_DRV_GRF_OFFSET 0x200 #define RK3568_DRV_BITS_PER_PIN 8 @@ -2495,6 +2639,10 @@ static int rockchip_set_drive_perpin(str rmask_bits = RK3588_DRV_BITS_PER_PIN; ret = strength; goto config; + } else if (ctrl->type == RK3528) { + rmask_bits = RK3528_DRV_BITS_PER_PIN; + ret = (1 << (strength + 1)) - 1; + goto config; } else if (ctrl->type == RK3568) { rmask_bits = RK3568_DRV_BITS_PER_PIN; ret = (1 << (strength + 1)) - 1; @@ -2639,6 +2787,7 @@ static int rockchip_get_pull(struct rock case RK3328: case RK3368: case RK3399: + case RK3528: case RK3568: case RK3576: case RK3588: @@ -2699,6 +2848,7 @@ static int rockchip_set_pull(struct rock case RK3328: case RK3368: case RK3399: + case RK3528: case RK3568: case RK3576: case RK3588: @@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid( case RK3328: case RK3368: case RK3399: + case RK3528: case RK3568: case RK3576: case RK3588: @@ -4084,6 +4235,49 @@ static struct rockchip_pin_ctrl rk3399_p .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; +static struct rockchip_pin_bank rk3528_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20020, 0x20028, 0x20030, 0x20038), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x30040, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20060, 0x20068, 0x20070, 0), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10080, 0x10088, 0x10090, 0x10098), +}; + +static struct rockchip_pin_ctrl rk3528_pin_ctrl __maybe_unused = { + .pin_banks = rk3528_pin_banks, + .nr_banks = ARRAY_SIZE(rk3528_pin_banks), + .label = "RK3528-GPIO", + .type = RK3528, + .pull_calc_reg = rk3528_calc_pull_reg_and_bit, + .drv_calc_reg = rk3528_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3568_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, @@ -4208,6 +4402,8 @@ static const struct of_device_id rockchi .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl }, + { .compatible = "rockchip,rk3528-pinctrl", + .data = &rk3528_pin_ctrl }, { .compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl }, { .compatible = "rockchip,rk3576-pinctrl", --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { RK3328, RK3368, RK3399, + RK3528, RK3568, RK3576, RK3588,