From 8d111d707f71bc17c616b0bcca327ee0a3db50e8 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 2 Nov 2020 19:03:59 +0100 Subject: [PATCH] clk: qcom: ipq8074: fix PCI-E clock oops Fix PCI-E clock related kernel oops that are causes by missing parent_names. Without the use of parent_names kernel will panic on clk_core_get_parent_by_index() due to a NULL pointer. Without this earlycon is needed to even catch the OOPS as it will reset the board before serial is initialized. Fixes: f0cfcf1ade20 ("clk: qcom: ipq8074: Add missing clocks for pcie") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie0_rchng_clk_src", - .parent_hws = (const struct clk_hw *[]) { - &gpll0.clkr.hw }, + .parent_names = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -4344,8 +4343,8 @@ static struct clk_branch gcc_pcie0_rchng .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_rchng_clk", - .parent_hws = (const struct clk_hw *[]){ - &pcie0_rchng_clk_src.clkr.hw, + .parent_names = (const char *[]){ + "pcie0_rchng_clk_src", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -4362,8 +4361,8 @@ static struct clk_branch gcc_pcie0_axi_s .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_axi_s_bridge_clk", - .parent_hws = (const struct clk_hw *[]){ - &pcie0_axi_clk_src.clkr.hw, + .parent_names = (const char *[]){ + "pcie0_axi_clk_src" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT,