From 5f707d3ff1b22c089253e39906b5edeeb5f10fdc Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Fri, 3 Apr 2020 15:31:59 +0530 Subject: [PATCH] clk: qcom: ipq8074: SW workaround for UBI PLL lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some chip’s Huyara PLL is unable to lock in 5 us and generating UBI PLL lock error. WARNING: CPU: 1 PID: 625 at drivers/clk/qcom/clk-alpha-pll.c:114 wait_for_pll+0xbc/0xe0() ubi32_pll_main failed to enable! CPU: 1 PID: 625 Comm: kmodloader Not tainted 4.4.60 #1 Hardware name: Generic DT based system (unwind_backtrace) from [<8021b550>] (show_stack+0x10/0x14) (show_stack) from [<803f6b24>] (dump_stack+0x80/0xa0) (dump_stack) from [<80228ff0>] (warn_slowpath_common+0x84/0xb0) (warn_slowpath_common) from [<80229048>] (warn_slowpath_fmt+0x2c/0x3c) (warn_slowpath_fmt) from [<8054d53c>] (wait_for_pll+0xbc/0xe0) (wait_for_pll) from [<8054d6cc>] (clk_alpha_pll_enable+0xe0/0x128) (clk_alpha_pll_enable) from [<80547b68>] (clk_core_enable+0x68/0x98) (clk_core_enable) from [<80547b48>] (clk_core_enable+0x48/0x98) This is BUG in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. Change-Id: Ib5473f4011e3410515f382b2445bee2d66dd654a Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/gcc-ipq8074.c | 3 +++ 1 file changed, 3 insertions(+) --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -5068,6 +5068,9 @@ static int gcc_ipq8074_probe(struct plat /* Disable SW_COLLAPSE for USB1 GDSCR */ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); + /* SW Workaround for UBI Huayra PLL */ + regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config);