From 474740fac667ccf7a6b3c748d851e5ed364d59eb Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Mon, 4 Sep 2017 15:00:10 +0530 Subject: [PATCH 1/3] clk: qcom: fix wrong RCG clock rate for high parent freq If the parent clock rate is greater than unsigned long max divided by 2 then the integer overflow is happening while calculating the clock rate. Since RCG2 uses half integer dividers, the clock rate is first being multiplied by 2 followed by division and this multiplication leads to overflow. Change-Id: I4e4f41b4a539446b962eb684761a3aad6f8a8977 Signed-off-by: Abhishek Sahu (cherry picked from commit 9cfedaf465eb18ef31e4d677cba5f3147fe6d430) Signed-off-by: Praveenkumar I Change-Id: I69b78616f468bb7a9647c7994a8579b97c376d4e --- drivers/clk/qcom/clk-rcg2.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -145,18 +145,18 @@ static int clk_rcg2_set_parent(struct cl * hid_div n */ static unsigned long -calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) +calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div) { + u64 rate = parent_rate; + if (hid_div) { rate *= 2; - rate /= hid_div + 1; + do_div(rate, hid_div + 1); } if (mode) { - u64 tmp = rate; - tmp *= m; - do_div(tmp, n); - rate = tmp; + rate *= m; + do_div(rate, n); } return rate;