From 050b312654523aac9495eae3cf7bfa868fd981ce Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Fri, 3 Jan 2025 15:31:38 +0800 Subject: [PATCH 3/3] arm64: dts: qcom: ipq9574: Update xo_board_clk to use fixed factor clock xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-5-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -131,8 +131,13 @@ clock-mult = <1>; }; +/* + * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -32,7 +32,8 @@ }; xo_board_clk: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; };