mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-06-11 10:42:04 +08:00
57 lines
1.4 KiB
Diff
57 lines
1.4 KiB
Diff
This adds the otp node to the rk3576 soc devicetree including the
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individual fields we know about.
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 39 ++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1173,6 +1173,45 @@
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status = "disabled";
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};
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+ otp: otp@2a580000 {
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+ compatible = "rockchip,rk3576-otp";
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+ reg = <0x0 0x2a580000 0x0 0x400>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
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+ <&cru CLK_OTP_PHY_G>;
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+ clock-names = "otp", "apb_pclk", "phy";
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+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
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+ reset-names = "otp", "apb";
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+
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+ /* Data cells */
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+ cpu_code: cpu-code@2 {
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+ reg = <0x02 0x2>;
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+ };
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+ otp_cpu_version: cpu-version@5 {
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+ reg = <0x05 0x1>;
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+ bits = <3 3>;
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+ };
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+ otp_id: id@a {
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+ reg = <0x0a 0x10>;
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+ };
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+ cpub_leakage: cpub-leakage@1e {
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+ reg = <0x1e 0x1>;
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+ };
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+ cpul_leakage: cpul-leakage@1f {
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+ reg = <0x1f 0x1>;
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+ };
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+ npu_leakage: npu-leakage@20 {
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+ reg = <0x20 0x1>;
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+ };
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+ gpu_leakage: gpu-leakage@21 {
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+ reg = <0x21 0x1>;
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+ };
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+ log_leakage: log-leakage@22 {
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+ reg = <0x22 0x1>;
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+ };
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+ };
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+
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gic: interrupt-controller@2a701000 {
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compatible = "arm,gic-400";
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reg = <0x0 0x2a701000 0 0x10000>,
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