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Updating the spi-qpic-snand driver with the latest patches sent upstream and remove custom patches. These patches add error handling fixes, use of right read location in read ops, removal of unused variable, ability to read user config and nand chip requirements, and support for 8bits ECC strength. Tested on: Gl.iNet GL-B3000 & Linksys MR5500, MX2000, MX5500, SPNMX56 Signed-off-by: George Moussalem <george.moussalem@outlook.com> Signed-off-by: Robert Marko <robimarko@gmail.com>
47 lines
1.6 KiB
Diff
47 lines
1.6 KiB
Diff
From 2e1ab53e8fcf708db51f560f7846802d406ee57d Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Thu, 15 May 2025 22:47:43 +0200
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Subject: [PATCH] spi: spi-qpic-snand: default to 4-bit ECC
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There are NAND IC-s that define 1-bit ECC as the minimal strength,
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however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
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ECC.
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Since most of these chips also support 4-bit ECC just fine, instead of
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erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.
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Fixes: 01b72ce61e8f ("qualcommax: ipq50xx: remove ECC user config from board files")
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/spi/spi-qpic-snand.c | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -296,6 +296,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
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ecc_cfg->spare_bytes = 2;
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break;
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+ case 1:
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+ case 2:
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+ /*
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+ * Many chips have set a minimum ECC strength requirement
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+ * lower than 4-bits but also support higher strength, so
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+ * check if ecc_cfg was set by chip reqs and try 4-bits.
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+ */
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+ if (reqs->strength) {
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+ dev_warn(snandc->dev,
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+ "ECC strength requirement of %u-bit(s) is unsupported, trying 4-bits\n",
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+ reqs->strength);
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+ ecc_cfg->ecc_mode = ECC_MODE_4BIT;
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+ ecc_cfg->ecc_bytes_hw = 7;
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+ ecc_cfg->spare_bytes = 4;
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+ break;
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+ } else
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+ fallthrough;
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+
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default:
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dev_err(snandc->dev,
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"only 4 or 8 bits ECC strength is supported\n");
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