lede/target/linux/qualcommax/patches-6.6/0401-spi-spi-qpic-snand-default-to-4-bit-ECC.patch
George Moussalem 6c60a311fb spi-qpic-snand: sync patch from upstream
Updating the spi-qpic-snand driver with the latest patches sent
upstream and remove custom patches.
These patches add error handling fixes, use of right read location in
read ops, removal of unused variable, ability to read user config and
nand chip requirements, and support for 8bits ECC strength.

Tested on: Gl.iNet GL-B3000 & Linksys MR5500, MX2000, MX5500, SPNMX56

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
2025-05-27 23:00:15 +08:00

47 lines
1.6 KiB
Diff

From 2e1ab53e8fcf708db51f560f7846802d406ee57d Mon Sep 17 00:00:00 2001
From: George Moussalem <george.moussalem@outlook.com>
Date: Thu, 15 May 2025 22:47:43 +0200
Subject: [PATCH] spi: spi-qpic-snand: default to 4-bit ECC
There are NAND IC-s that define 1-bit ECC as the minimal strength,
however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
ECC.
Since most of these chips also support 4-bit ECC just fine, instead of
erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.
Fixes: 01b72ce61e8f ("qualcommax: ipq50xx: remove ECC user config from board files")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/spi/spi-qpic-snand.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -296,6 +296,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
ecc_cfg->spare_bytes = 2;
break;
+ case 1:
+ case 2:
+ /*
+ * Many chips have set a minimum ECC strength requirement
+ * lower than 4-bits but also support higher strength, so
+ * check if ecc_cfg was set by chip reqs and try 4-bits.
+ */
+ if (reqs->strength) {
+ dev_warn(snandc->dev,
+ "ECC strength requirement of %u-bit(s) is unsupported, trying 4-bits\n",
+ reqs->strength);
+ ecc_cfg->ecc_mode = ECC_MODE_4BIT;
+ ecc_cfg->ecc_bytes_hw = 7;
+ ecc_cfg->spare_bytes = 4;
+ break;
+ } else
+ fallthrough;
+
default:
dev_err(snandc->dev,
"only 4 or 8 bits ECC strength is supported\n");