mirror of
https://github.com/coolsnowwolf/lede.git
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a462d2b757
* target: add phytium support * kernel/video: add phytium platform ARM GPU support * config: add EFI support to phytium armv8 * target: phytium: remove rtl8821cs driver * target: phytium: refresh dts
201 lines
7.5 KiB
C
Executable File
201 lines
7.5 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Phytium SD Card Interface driver
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*
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* Copyright (c) 2019-2023, Phytium Technology Co.,Ltd.
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*/
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/*---------------------------------------------------------------------------*/
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/* Common Definition */
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/*---------------------------------------------------------------------------*/
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#define MAX_BD_NUM 0x1000
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#define SD_BLOCK_SIZE 512
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/*---------------------------------------------------------------------------*/
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/* Register Offset */
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/*---------------------------------------------------------------------------*/
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#define SDCI_CONTROLLER 0x00 /* controller config reg */
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#define SDCI_ARGUMENT 0x04 /* argument reg */
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#define SDCI_COMMAND 0x08 /* command reg */
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#define SDCI_CLOCK_D 0x0C /* clock divide reg */
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#define SDCI_SOFTWARE 0x10 /* controller reset reg */
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#define SDCI_POWER 0X14 /* POWRE CONTROL REG */
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#define SDCI_TIMEOUT_CMD 0x18 /* cmd timeout config reg */
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#define SDCI_TIMEOUT_DATA 0x1C /* data timeout reg */
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#define SDCI_NORMAL_ISER 0x20 /* normal ISR config reg */
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#define SDCI_ERROR_ISER 0x24 /* erroe ISR config reg */
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#define SDCI_BD_ISER 0x28 /* BD ISR config reg */
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#define SDCI_CAPA 0x2C /* BD ISR config reg */
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#define SDCI_SD_DRV 0x30 /* SD card driving phase position reg */
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#define SDCI_SD_SAMP 0x34 /* SD card sampling phase position reg */
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#define SDCI_SD_SEN 0x38 /* SD card detection reg */
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#define SDCI_HDS_AXI 0x3C /* AXI boundary config reg */
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#define SDCI_BD_RX 0x40 /* BD rx addr reg */
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#define SDCI_BD_TX 0x60 /* BD tx addr reg */
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#define SDCI_BLK_CNT 0x80 /* r/w block num reg */
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#define SDCI_NORMAL_ISR 0xC0 /* normal ISR status reg */
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#define SDCI_ERROR_ISR 0xC4 /* error ISR status reg */
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#define SDCI_BD_ISR 0xC8 /* BD ISR status reg */
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#define SDCI_BD_STATUS 0xCC /* BD descriptor status reg */
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#define SDCI_STATUS 0xD0 /* status reg */
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#define SDCI_BLOCK 0xD4 /* block len reg */
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#define SDCI_RESP0 0xE0 /* response reg0 */
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#define SDCI_RESP1 0xE4 /* response reg1 */
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#define SDCI_RESP2 0xE8 /* response reg2 */
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#define SDCI_RESP3 0XEC /* response reg3 */
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/*---------------------------------------------------------------------------*/
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/* Register Mask */
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/*---------------------------------------------------------------------------*/
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/* SDCI_CONTROLLER mask */
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#define SDCI_CONTROLLER_ECRCWR (0x1 << 0) /* RW */
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#define SDCI_CONTROLLER_ECRCRD (0x1 << 1) /* RW */
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#define SDCI_CONTROLLER_RESEDE (0x1 << 2) /* RW */
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#define SDCI_CONTROLLER_PERMDR (0x3 << 8) /* RW */
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#define SDCI_CONTROLLER_PERMDX (0x3 << 10) /* RW */
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/* SDCI_SOFTWARE mask */
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#define SDCI_SOFTWARE_SRST (0x1 << 0) /* RW */
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#define SDCI_SOFTWARE_SCRST (0x1 << 1) /* RW */
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#define SDCI_SOFTWARE_BDRST (0x1 << 2) /* RW */
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#define SDCI_SOFTWARE_CFCLF (0x1 << 3) /* RW */
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#define SDCI_SOFTWARE_SDRST (0x1 << 4) /* RW */
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/* SDCI_NORMAL_ISER mask */
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#define SDCI_SDCI_NORMAL_ISER_ECC_EN (0x1 << 0) /* RW */
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#define SDCI_SDCI_NORMAL_ISER_ECR (0x1 << 1) /* RW */
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#define SDCI_SDCI_NORMAL_ISER_ECI (0x1 << 2) /* RW */
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#define SDCI_SDCI_NORMAL_ISER_EEI_EN (0x1 << 15) /* RW */
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/* SDCI_NORMAL_ISR mask */
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#define SDCI_NORMAL_ISR_CC (0x1 << 0) /* R */
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#define SDCI_NORMAL_ISR_CR (0x1 << 1) /* R */
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#define SDCI_NORMAL_ISR_CI (0x1 << 2) /* R */
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#define SDCI_NORMAL_ISR_TIMEOUT (0x1 << 3) /* R */
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#define SDCI_NORMAL_ISR_EI (0x1 << 15) /* R */
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/* SDCI_ERROR_ISER mask */
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#define SDCI_ERROR_ISER_ECTE_EN (0x1 << 0) /* RW */
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#define SDCI_ERROR_ISR_CCRCE_EN (0x1 << 1) /* RW */
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#define SDCI_ERROR_ISR_CIR_EN (0x1 << 3) /* RW */
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#define SDCI_ERROR_ISR_CNR_EN (0x1 << 4) /* RW */
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/* SDCI_ERROR_ISR mask */
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#define SDCI_ERROR_ISR_CTE (0x1 << 0) /* R */
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#define SDCI_ERROR_ISR_CCRCE (0x1 << 1) /* R */
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#define SDCI_ERROR_ISR_CIR (0x1 << 3) /* R */
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#define SDCI_ERROR_ISR_CNR (0x1 << 4) /* R */
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/* SDCI_BD_ISER mask */
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#define SDCI_BD_ISER_ETRS_EN (0x1 << 8) /* RW */
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#define SDCI_BD_ISER_DATFRAX_EN (0x1 << 7) /* RW */
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/* SDCI_BD_ISR mask */
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#define SDCI_BD_ISR_TRS_W (0x1 << 0) /* R */
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#define SDCI_BD_ISR_TRS_R (0x1 << 8) /* R */
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#define SDCI_BD_ISR_EDTE (0x1 << 3) /* R */
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#define SDCI_BD_ISR_DAIS (0x1 << 15) /* R */
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#define SDCI_BD_ISR_DATFRAX (0x1 << 7) /* R */
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/* SDCI_HDS_AXI mask */
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#define SDCI_HDS_AXI_AWDOMAIN (0x1 << 0) /* RW */
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#define SDCI_HDS_AXI_ARDOMAIN (0x1 << 12) /* RW */
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#define SDCI_HDS_AXI_AWCACHE (0x6 << 24) /* RW */
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#define SDCI_HDS_AXI_ARCACHE (0xB << 28) /* RW */
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/* SDCI_STATUS mask */
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#define SDCI_STATUS_CMD_BUSY (0x0 << 0) /* R */
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#define SDCI_STATUS_CMD_READY (0x1 << 0) /* R */
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#define SDCI_STATUS_IDIE (0x1 << 12) /* R */
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#define SDCI_CARD_BUSY_IN_PRG (0x1 << 20) /* R D0 BUSY:0,IDLE:1 */
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/* SDCI_STATUS */
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#define SDCI_STATUS_CDSL (0x1 << 19) /* R */
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/*---------------------------------------------------------------------------*/
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/* Register Value */
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/*---------------------------------------------------------------------------*/
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#define SDCI_SD_DRV_VALUE 0
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#define SDCI_SD_SAMP_VALUE_MAX 50
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#define SDCI_SD_SAMP_VALUE_MIN 0
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#define SDCI_TIMEOUT_CMD_VALUE 0xFFFFFFFF
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#define SDCI_TIMEOUT_DATA_VALUE 0xFFFFFFFF
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#define SDCI_POWER_ON 1
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#define SDCI_POWER_OFF 0
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#define SDCI_CMD_TIMEOUT 10
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#define SDCI_DAT_TIMEOUT 5000
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#define SDCI_CMD_TYPE_ADTC 0x2
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#define SDCI_F_MIN 400000
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#define SDCI_F_MAX 25000000
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#define SDCI_SEN_CREFR_VAL (0x1 << 1)
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#define SDCI_SEN_DEBNCE_VAL (0xB << 8)
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#define CARD_CURRENT_STATE (0xF << 9)
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#define CARD_PRG_STATE (0x7 << 9)
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#define CARD_TRAN_STATE (0x4 << 9)
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#define SDCI_CMD13_OK 1
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#define SDCI_CMD13_FAILED 0
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#define ERR_TIMEOUT (0x1 << 0)
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#define ERR_CARD_ABSENT (0x1 << 1)
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#define ERR_CMD_RESPONED (0x1 << 2)
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/*---------------------------------------------------------------------------*/
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/* Structure Type */
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/*---------------------------------------------------------------------------*/
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struct phytium_sdci_dma {
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struct scatterlist *sg;
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u32 *buf;
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dma_addr_t bd_addr;
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size_t bytes;
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};
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enum adtc_type {
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COMMOM_ADTC = 0,
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BLOCK_RW_ADTC,
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};
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struct phytium_sdci_host {
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struct device *dev;
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struct mmc_host *mmc;
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u32 caps;
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spinlock_t lock;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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int error;
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void __iomem *base;
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struct phytium_sdci_dma dma_rx;
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struct phytium_sdci_dma dma_tx;
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u32 *sg_virt_addr;
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enum adtc_type adtc_type;
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struct timer_list hotplug_timer;
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struct delayed_work req_timeout;
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u32 cmd_timeout;
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u32 data_timeout;
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int irq;
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int irq_err;
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int irq_bd;
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struct clk *src_clk;
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unsigned long clk_rate;
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unsigned long clk_div;
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unsigned long real_rate;
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u32 current_rca;
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bool is_multi_rw_only_one_blkcnt;
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};
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