mirror of
https://github.com/coolsnowwolf/lede.git
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a462d2b757
* target: add phytium support * kernel/video: add phytium platform ARM GPU support * config: add EFI support to phytium armv8 * target: phytium: remove rtl8821cs driver * target: phytium: refresh dts
162 lines
5.0 KiB
C
162 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright Everest Semiconductor Co.,Ltd
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* Phytium Information Technology Co.,Ltd
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*
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* Author: David Yang <yangxiaohua@everest-semi.com>
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* Yiqun Zhang <zhangyiqun@phytium.com.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _ES8336_H
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#define _ES8336_H
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/* ES8336 register space */
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/*
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* RESET Control
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*/
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#define ES8336_RESET_REG00 0x00
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/*
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* Clock Managerment
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*/
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#define ES8336_CLKMGR_CLKSW_REG01 0x01
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#define ES8336_CLKMGR_CLKSEL_REG02 0x02
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#define ES8336_CLKMGR_ADCOSR_REG03 0x03
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#define ES8336_CLKMGR_ADCDIV1_REG04 0x04
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#define ES8336_CLKMGR_ADCDIV2_REG05 0x05
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#define ES8336_CLKMGR_DACDIV1_REG06 0x06
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#define ES8336_CLKMGR_DACDIV2_REG07 0x07
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#define ES8336_CLKMGR_CPDIV_REG08 0x08
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/*
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* SDP Control
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*/
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#define ES8336_SDP_MS_BCKDIV_REG09 0x09
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#define ES8336_SDP_ADCFMT_REG0A 0x0a
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#define ES8336_SDP_DACFMT_REG0B 0x0b
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/*
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* System Control
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*/
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#define ES8336_SYS_VMIDSEL_REG0C 0x0c
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#define ES8336_SYS_PDN_REG0D 0x0d
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#define ES8336_SYS_LP1_REG0E 0x0e
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#define ES8336_SYS_LP2_REG0F 0x0f
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#define ES8336_SYS_VMIDLOW_REG10 0x10
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#define ES8336_SYS_VSEL_REG11 0x11
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#define ES8336_SYS_REF_REG12 0x12
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/*
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* HP Mixer
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*/
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#define ES8336_HPMIX_SEL_REG13 0x13
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#define ES8336_HPMIX_SWITCH_REG14 0x14
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#define ES8336_HPMIX_PDN_REG15 0x15
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#define ES8336_HPMIX_VOL_REG16 0x16
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/*
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* Charge Pump Headphone driver
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*/
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#define ES8336_CPHP_OUTEN_REG17 0x17
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#define ES8336_CPHP_ICAL_VOL_REG18 0x18
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#define ES8336_CPHP_PDN1_REG19 0x19
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#define ES8336_CPHP_PDN2_REG1A 0x1a
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#define ES8336_CPHP_LDOCTL_REG1B 0x1b
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/*
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* Calibration
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*/
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#define ES8336_CAL_TYPE_REG1C 0x1c
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#define ES8336_CAL_SET_REG1D 0x1d
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#define ES8336_CAL_HPLIV_REG1E 0x1e
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#define ES8336_CAL_HPRIV_REG1F 0x1f
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#define ES8336_CAL_HPLMV_REG20 0x20
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#define ES8336_CAL_HPRMV_REG21 0x21
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/*
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* ADC Control
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*/
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#define ES8336_ADC_PDN_LINSEL_REG22 0x22
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#define ES8336_ADC_PGAGAIN_REG23 0x23
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#define ES8336_ADC_D2SEPGA_REG24 0x24
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#define ES8336_ADC_DMIC_REG25 0x25
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#define ES8336_ADC_MUTE_REG26 0x26
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#define ES8336_ADC_VOLUME_REG27 0x27
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#define ES8336_ADC_ALC1_REG29 0x29
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#define ES8336_ADC_ALC2_REG2A 0x2a
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#define ES8336_ADC_ALC3_REG2B 0x2b
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#define ES8336_ADC_ALC4_REG2C 0x2c
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#define ES8336_ADC_ALC5_REG2D 0x2d
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#define ES8336_ADC_ALC6_REG2E 0x2e
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/*
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* DAC Control
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*/
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#define ES8336_DAC_PDN_REG2F 0x2f
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#define ES8336_DAC_SET1_REG30 0x30
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#define ES8336_DAC_SET2_REG31 0x31
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#define ES8336_DAC_SET3_REG32 0x32
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#define ES8336_DAC_VOLL_REG33 0x33
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#define ES8336_DAC_VOLR_REG34 0x34
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/*
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* GPIO
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*/
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#define ES8336_GPIO_SEL_REG4D 0x4D
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#define ES8336_GPIO_DEBUNCE_INT_REG4E 0x4E
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#define ES8336_GPIO_FLAG 0x4F
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/*
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* TEST MODE
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*/
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#define ES8336_TESTMODE_REG50 0x50
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#define ES8336_TEST1_REG51 0x51
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#define ES8336_TEST2_REG52 0x52
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#define ES8336_TEST3_REG53 0x53
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#define ES8336_IFACE ES8336_SDP_MS_BCKDIV_REG09
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#define ES8336_ADC_IFACE ES8336_SDP_ADCFMT_REG0A
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#define ES8336_DAC_IFACE ES8336_SDP_DACFMT_REG0B
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#define ES8336_REGNUM 84
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/* REGISTER 0X01 CLOCK MANAGER */
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#define ES8336_CLKMGR_MCLK_DIV_MASK (0X1<<7)
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#define ES8336_CLKMGR_MCLK_DIV_NML (0X0<<7)
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#define ES8336_CLKMGR_MCLK_DIV_1 (0X1<<7)
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#define ES8336_CLKMGR_ADC_MCLK_MASK (0X1<<3)
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#define ES8336_CLKMGR_ADC_MCLK_EN (0X1<<3)
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#define ES8336_CLKMGR_ADC_MCLK_DIS (0X0<<3)
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#define ES8336_CLKMGR_DAC_MCLK_MASK (0X1<<2)
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#define ES8336_CLKMGR_DAC_MCLK_EN (0X1<<2)
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#define ES8336_CLKMGR_DAC_MCLK_DIS (0X0<<2)
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#define ES8336_CLKMGR_ADC_ANALOG_MASK (0X1<<1)
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#define ES8336_CLKMGR_ADC_ANALOG_EN (0X1<<1)
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#define ES8336_CLKMGR_ADC_ANALOG_DIS (0X0<<1)
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#define ES8336_CLKMGR_DAC_ANALOG_MASK (0X1<<0)
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#define ES8336_CLKMGR_DAC_ANALOG_EN (0X1<<0)
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#define ES8336_CLKMGR_DAC_ANALOG_DIS (0X0<<0)
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/* REGISTER 0X0A */
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#define ES8336_ADCWL_MASK (0x7 << 2)
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#define ES8336_ADCWL_32 (0x4 << 2)
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#define ES8336_ADCWL_24 (0x0 << 2)
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#define ES8336_ADCWL_20 (0x1 << 2)
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#define ES8336_ADCWL_18 (0x2 << 2)
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#define ES8336_ADCWL_16 (0x3 << 2)
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#define ES8336_ADCFMT_MASK (0x3 << 0)
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#define ES8336_ADCFMT_I2S (0x0 << 0)
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#define ES8336_ADCWL_LEFT (0x1 << 0)
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#define ES8336_ADCWL_RIGHT (0x2 << 0)
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#define ES8336_ADCWL_PCM (0x3 << 0)
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/* REGISTER 0X0B */
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#define ES8336_DACWL_MASK (0x7 << 2)
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#define ES8336_DACWL_32 (0x4 << 2)
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#define ES8336_DACWL_24 (0x0 << 2)
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#define ES8336_DACWL_20 (0x1 << 2)
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#define ES8336_DACWL_18 (0x2 << 2)
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#define ES8336_DACWL_16 (0x3 << 2)
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#define ES8336_DACFMT_MASK (0x3 << 0)
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#define ES8336_DACFMT_I2S (0x0 << 0)
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#define ES8336_DACWL_LEFT (0x1 << 0)
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#define ES8336_DACWL_RIGHT (0x2 << 0)
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#define ES8336_DACWL_PCM (0x3 << 0)
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#endif
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