mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-06-10 14:22:05 +08:00
47 lines
1.5 KiB
Diff
47 lines
1.5 KiB
Diff
From ce4c7eea1b6f05723240aadc5e1c240d26a6ef88 Mon Sep 17 00:00:00 2001
|
|
From: Mantas Pucka <mantas@8devices.com>
|
|
Date: Mon, 31 Mar 2025 15:39:59 +0300
|
|
Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config
|
|
|
|
Currently there is no configuration to derive 25/125MHz port5 clock
|
|
from uniphy1 running at 125MHz. This is needed for SGMII mode when
|
|
port5 is using uniphy1.
|
|
|
|
Fix this by adding option such clock config option.
|
|
|
|
Signed-off-by: Mantas Pucka <mantas@8devices.com>
|
|
---
|
|
drivers/clk/qcom/nsscc-ipq9574.c | 4 ++++
|
|
1 file changed, 4 insertions(+)
|
|
|
|
--- a/drivers/clk/qcom/nsscc-ipq9574.c
|
|
+++ b/drivers/clk/qcom/nsscc-ipq9574.c
|
|
@@ -387,11 +387,13 @@ static const struct freq_multi_tbl ftbl_
|
|
|
|
static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
|
|
C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
|
|
+ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
|
|
C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
|
|
};
|
|
|
|
static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
|
|
C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
|
|
+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
|
|
C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
|
|
};
|
|
|
|
@@ -412,11 +414,13 @@ static const struct freq_multi_tbl ftbl_
|
|
|
|
static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
|
|
C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
|
|
+ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
|
|
C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
|
|
};
|
|
|
|
static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
|
|
C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
|
|
+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
|
|
C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
|
|
};
|
|
|