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The MediaTek Ethernet PHY drivers are going to be used by multiple targets (airoha, mediatek, ramips). Add generic backports of changes required for recently added Ethernet PHYs. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
130 lines
4.0 KiB
Diff
130 lines
4.0 KiB
Diff
From 4590c8bc10951feee3e439bf7fff1b458c2e6fad Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 10 Apr 2025 12:04:04 +0200
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Subject: [PATCH 17/20] net: phy: mediatek: add Airoha PHY ID to SoC driver
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Airoha AN7581 SoC ship with a Switch based on the MT753x Switch embedded
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in other SoC like the MT7581 and the MT7988. Similar to these they
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require configuring some pin to enable LED PHYs.
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Add support for the PHY ID for the Airoha embedded Switch and define a
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simple probe function to toggle these pins. Also fill the LED functions
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and add dedicated function to define LED polarity.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Link: https://patch.msgid.link/20250410100410.348-2-ansuelsmth@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/mediatek/Kconfig | 4 +-
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drivers/net/phy/mediatek/mtk-ge-soc.c | 62 +++++++++++++++++++++++++++
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2 files changed, 65 insertions(+), 1 deletion(-)
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--- a/drivers/net/phy/mediatek/Kconfig
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+++ b/drivers/net/phy/mediatek/Kconfig
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@@ -15,7 +15,9 @@ config MEDIATEK_GE_PHY
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config MEDIATEK_GE_SOC_PHY
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tristate "MediaTek SoC Ethernet PHYs"
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- depends on (ARM64 && ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST
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+ depends on ARM64 || COMPILE_TEST
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+ depends on ARCH_AIROHA || (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || \
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+ COMPILE_TEST
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select MTK_NET_PHYLIB
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help
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Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
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--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
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+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
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@@ -10,8 +10,11 @@
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#include "mtk.h"
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+#define MTK_PHY_MAX_LEDS 2
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+
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#define MTK_GPHY_ID_MT7981 0x03a29461
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#define MTK_GPHY_ID_MT7988 0x03a29481
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+#define MTK_GPHY_ID_AN7581 0x03a294c1
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#define MTK_EXT_PAGE_ACCESS 0x1f
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#define MTK_PHY_PAGE_STANDARD 0x0000
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@@ -1405,6 +1408,53 @@ static int mt7981_phy_probe(struct phy_d
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return mt798x_phy_calibration(phydev);
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}
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+static int an7581_phy_probe(struct phy_device *phydev)
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+{
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+ struct mtk_socphy_priv *priv;
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+ struct pinctrl *pinctrl;
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+
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+ /* Toggle pinctrl to enable PHY LED */
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+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
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+ if (IS_ERR(pinctrl))
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+ dev_err(&phydev->mdio.bus->dev,
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+ "Failed to setup PHY LED pinctrl\n");
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+
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+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ phydev->priv = priv;
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+
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+ return 0;
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+}
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+
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+static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
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+ unsigned long modes)
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+{
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+ u32 mode;
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+ u16 val;
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+
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+ if (index >= MTK_PHY_MAX_LEDS)
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+ return -EINVAL;
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+
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+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
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+ switch (mode) {
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+ case PHY_LED_ACTIVE_LOW:
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+ val = MTK_PHY_LED_ON_POLARITY;
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+ break;
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+ case PHY_LED_ACTIVE_HIGH:
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+ val = 0;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+ }
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+
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+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
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+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
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+ MTK_PHY_LED_ON_POLARITY, val);
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+}
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+
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static struct phy_driver mtk_socphy_driver[] = {
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{
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PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
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@@ -1440,6 +1490,17 @@ static struct phy_driver mtk_socphy_driv
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.led_hw_control_set = mt798x_phy_led_hw_control_set,
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.led_hw_control_get = mt798x_phy_led_hw_control_get,
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},
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+ {
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+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581),
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+ .name = "Airoha AN7581 PHY",
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+ .probe = an7581_phy_probe,
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+ .led_blink_set = mt798x_phy_led_blink_set,
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+ .led_brightness_set = mt798x_phy_led_brightness_set,
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+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
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+ .led_hw_control_set = mt798x_phy_led_hw_control_set,
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+ .led_hw_control_get = mt798x_phy_led_hw_control_get,
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+ .led_polarity_set = an7581_phy_led_polarity_set,
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+ },
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};
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module_phy_driver(mtk_socphy_driver);
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@@ -1447,6 +1508,7 @@ module_phy_driver(mtk_socphy_driver);
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static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
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{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
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{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
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+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) },
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{ }
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};
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