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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
99 lines
3.3 KiB
Diff
99 lines
3.3 KiB
Diff
From d1f1570f3d6db5d35642092a671812e62bfba79d Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Tue, 30 Apr 2024 12:12:10 +0530
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Subject: [PATCH] dt-bindings: interconnect: Add Qualcomm IPQ9574 support
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Add interconnect-cells to clock provider so that it can be
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used as icc provider.
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Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
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interfaces. This will be used by the gcc-ipq9574 driver
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that will for providing interconnect services using the
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icc-clk framework.
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Acked-by: Georgi Djakov <djakov@kernel.org>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Link: https://lore.kernel.org/r/20240430064214.2030013-3-quic_varada@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
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.../dt-bindings/interconnect/qcom,ipq9574.h | 59 +++++++++++++++++++
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2 files changed, 62 insertions(+)
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create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
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--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
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+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
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@@ -33,6 +33,9 @@ properties:
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- description: PCIE30 PHY3 pipe clock source
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- description: USB3 PHY pipe clock source
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+ '#interconnect-cells':
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+ const: 1
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+
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required:
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- compatible
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- clocks
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--- /dev/null
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+++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
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@@ -0,0 +1,59 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+#ifndef INTERCONNECT_QCOM_IPQ9574_H
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+#define INTERCONNECT_QCOM_IPQ9574_H
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+
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+#define MASTER_ANOC_PCIE0 0
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+#define SLAVE_ANOC_PCIE0 1
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+#define MASTER_SNOC_PCIE0 2
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+#define SLAVE_SNOC_PCIE0 3
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+#define MASTER_ANOC_PCIE1 4
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+#define SLAVE_ANOC_PCIE1 5
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+#define MASTER_SNOC_PCIE1 6
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+#define SLAVE_SNOC_PCIE1 7
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+#define MASTER_ANOC_PCIE2 8
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+#define SLAVE_ANOC_PCIE2 9
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+#define MASTER_SNOC_PCIE2 10
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+#define SLAVE_SNOC_PCIE2 11
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+#define MASTER_ANOC_PCIE3 12
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+#define SLAVE_ANOC_PCIE3 13
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+#define MASTER_SNOC_PCIE3 14
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+#define SLAVE_SNOC_PCIE3 15
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+#define MASTER_USB 16
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+#define SLAVE_USB 17
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+#define MASTER_USB_AXI 18
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+#define SLAVE_USB_AXI 19
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+#define MASTER_NSSNOC_NSSCC 20
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+#define SLAVE_NSSNOC_NSSCC 21
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+#define MASTER_NSSNOC_SNOC_0 22
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+#define SLAVE_NSSNOC_SNOC_0 23
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+#define MASTER_NSSNOC_SNOC_1 24
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+#define SLAVE_NSSNOC_SNOC_1 25
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+#define MASTER_NSSNOC_PCNOC_1 26
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+#define SLAVE_NSSNOC_PCNOC_1 27
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+#define MASTER_NSSNOC_QOSGEN_REF 28
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+#define SLAVE_NSSNOC_QOSGEN_REF 29
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+#define MASTER_NSSNOC_TIMEOUT_REF 30
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+#define SLAVE_NSSNOC_TIMEOUT_REF 31
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+#define MASTER_NSSNOC_XO_DCD 32
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+#define SLAVE_NSSNOC_XO_DCD 33
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+#define MASTER_NSSNOC_ATB 34
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+#define SLAVE_NSSNOC_ATB 35
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+#define MASTER_MEM_NOC_NSSNOC 36
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+#define SLAVE_MEM_NOC_NSSNOC 37
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+#define MASTER_NSSNOC_MEMNOC 38
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+#define SLAVE_NSSNOC_MEMNOC 39
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+#define MASTER_NSSNOC_MEM_NOC_1 40
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+#define SLAVE_NSSNOC_MEM_NOC_1 41
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+
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+#define MASTER_NSSNOC_PPE 0
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+#define SLAVE_NSSNOC_PPE 1
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+#define MASTER_NSSNOC_PPE_CFG 2
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+#define SLAVE_NSSNOC_PPE_CFG 3
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+#define MASTER_NSSNOC_NSS_CSR 4
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+#define SLAVE_NSSNOC_NSS_CSR 5
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+#define MASTER_NSSNOC_IMEM_QSB 6
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+#define SLAVE_NSSNOC_IMEM_QSB 7
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+#define MASTER_NSSNOC_IMEM_AHB 8
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+#define SLAVE_NSSNOC_IMEM_AHB 9
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+
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+#endif /* INTERCONNECT_QCOM_IPQ9574_H */
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