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d989a3256a
Refreshed patches for qualcommb/ipq95xx by running make target/linux/refresh after creating a .config containing: CONFIG_TARGET_qualcommbe=y CONFIG_TARGET_qualcommbe_ipq95xx=y CONFIG_TARGET_qualcommbe_ipq95xx_DEVICE_qcom_rdp433=y Signed-off-by: John Audia <therealgraysky@proton.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
From ac2bd244609c4423f96406005c9cee8b6952cd20 Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Fri, 25 Oct 2024 09:25:16 +0530
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Subject: [PATCH 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux
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clock
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Add support for gpll0_out_aux clock which acts as the parent for
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certain networking subsystem (nss) clocks.
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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---
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drivers/clk/qcom/gcc-ipq9574.c | 15 +++++++++++++++
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1 file changed, 15 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq9574.c
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+++ b/drivers/clk/qcom/gcc-ipq9574.c
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@@ -108,6 +108,20 @@ static struct clk_alpha_pll_postdiv gpll
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},
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};
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+static struct clk_alpha_pll_postdiv gpll0_out_aux = {
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+ .offset = 0x20000,
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+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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+ .width = 4,
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+ .clkr.hw.init = &(const struct clk_init_data) {
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+ .name = "gpll0_out_aux",
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+ .parent_hws = (const struct clk_hw *[]) {
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+ &gpll0_main.clkr.hw
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_alpha_pll_postdiv_ro_ops,
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+ },
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+};
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+
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static struct clk_alpha_pll gpll4_main = {
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.offset = 0x22000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
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@@ -4222,6 +4236,7 @@ static struct clk_regmap *gcc_ipq9574_cl
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[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
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[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
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[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
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+ [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
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};
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static const struct qcom_reset_map gcc_ipq9574_resets[] = {
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