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The MediaTek Ethernet PHY drivers are going to be used by multiple targets (airoha, mediatek, ramips). Add generic backports of changes required for recently added Ethernet PHYs. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
147 lines
5.3 KiB
Diff
147 lines
5.3 KiB
Diff
From 7e06c3dbfa5f1e39eba92eb79d854fab2a7ad5fe Mon Sep 17 00:00:00 2001
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From: Sky Huang <skylake.huang@mediatek.com>
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Date: Thu, 13 Feb 2025 16:05:49 +0800
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Subject: [PATCH 10/20] net: phy: mediatek: Change to more meaningful macros
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Replace magic number with more meaningful macros in mtk-ge.c.
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Also, move some common macros into mtk-phy-lib.c.
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Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://patch.msgid.link/20250213080553.921434-2-SkyLake.Huang@mediatek.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/mediatek/mtk-ge-soc.c | 1 -
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drivers/net/phy/mediatek/mtk-ge.c | 71 +++++++++++++++++++++------
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drivers/net/phy/mediatek/mtk.h | 2 +
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3 files changed, 57 insertions(+), 17 deletions(-)
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--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
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+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
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@@ -24,7 +24,6 @@
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#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
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#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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#define ANALOG_INTERNAL_OPERATION_MAX_US 20
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#define TXRESERVE_MIN 0
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--- a/drivers/net/phy/mediatek/mtk-ge.c
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+++ b/drivers/net/phy/mediatek/mtk-ge.c
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@@ -8,18 +8,38 @@
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#define MTK_GPHY_ID_MT7530 0x03a29412
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#define MTK_GPHY_ID_MT7531 0x03a29441
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-#define MTK_EXT_PAGE_ACCESS 0x1f
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-#define MTK_PHY_PAGE_STANDARD 0x0000
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-#define MTK_PHY_PAGE_EXTENDED 0x0001
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-#define MTK_PHY_PAGE_EXTENDED_2 0x0002
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-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
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-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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+#define MTK_PHY_PAGE_EXTENDED_1 0x0001
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+#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
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+#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
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+
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+#define MTK_PHY_PAGE_EXTENDED_2 0x0002
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+#define MTK_PHY_PAGE_EXTENDED_3 0x0003
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+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
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+
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+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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+
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+/* Registers on MDIO_MMD_VEND1 */
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+#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
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+#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
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+#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
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+#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
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+
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+#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
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+#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
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+
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+#define MTK_PHY_RXADC_CTRL_RG7 0xc6
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+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
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+
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+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
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+#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
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+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
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static void mtk_gephy_config_init(struct phy_device *phydev)
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{
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/* Enable HW auto downshift */
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- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
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+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
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+ MTK_PHY_AUX_CTRL_AND_STATUS,
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+ 0, MTK_PHY_ENABLE_DOWNSHIFT);
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/* Increase SlvDPSready time */
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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@@ -29,10 +49,20 @@ static void mtk_gephy_config_init(struct
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phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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/* Adjust 100_mse_threshold */
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- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
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-
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- /* Disable mcc */
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- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
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+ MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
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+ MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
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+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
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+ 0xff) |
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+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
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+ 0xff));
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+
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+ /* If echo time is narrower than 0x3, it will be regarded as noise */
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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+ MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
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+ MTK_MCC_NEARECHO_OFFSET_MASK,
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+ FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
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}
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static int mt7530_phy_config_init(struct phy_device *phydev)
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@@ -40,7 +70,8 @@ static int mt7530_phy_config_init(struct
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mtk_gephy_config_init(phydev);
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/* Increase post_update_timer */
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- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
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+ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
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+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
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return 0;
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}
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@@ -51,11 +82,19 @@ static int mt7531_phy_config_init(struct
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/* PHY link down power saving enable */
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phy_set_bits(phydev, 0x17, BIT(4));
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- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
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+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
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+ FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
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/* Set TX Pair delay selection */
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- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
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- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
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+ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
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+ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
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+ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
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+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
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+ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
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+ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
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+ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
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return 0;
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}
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--- a/drivers/net/phy/mediatek/mtk.h
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+++ b/drivers/net/phy/mediatek/mtk.h
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@@ -9,6 +9,8 @@
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#define _MTK_EPHY_H_
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#define MTK_EXT_PAGE_ACCESS 0x1f
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+#define MTK_PHY_PAGE_STANDARD 0x0000
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+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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/* Registers on MDIO_MMD_VEND2 */
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#define MTK_PHY_LED0_ON_CTRL 0x24
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