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The MediaTek Ethernet PHY drivers are going to be used by multiple targets (airoha, mediatek, ramips). Add generic backports of changes required for recently added Ethernet PHYs. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
123 lines
4.4 KiB
Diff
123 lines
4.4 KiB
Diff
From 7851c73a416b15aff6f9ada9c88affc5f48ff011 Mon Sep 17 00:00:00 2001
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From: Sky Huang <skylake.huang@mediatek.com>
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Date: Thu, 13 Feb 2025 16:05:52 +0800
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Subject: [PATCH 13/20] net: phy: mediatek: Add token ring clear bit operation
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support
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Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c,
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we clear some register bits via token ring, which were also implemented
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in three __phy_write(). Now we can do the same thing via
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__mtk_tr_clr_bits() helper.
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Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://patch.msgid.link/20250213080553.921434-5-SkyLake.Huang@mediatek.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/mediatek/mtk-ge-soc.c | 30 +++++++++++++++-----------
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drivers/net/phy/mediatek/mtk-phy-lib.c | 7 ++++++
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drivers/net/phy/mediatek/mtk.h | 2 ++
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3 files changed, 27 insertions(+), 12 deletions(-)
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--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
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+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
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@@ -76,6 +76,10 @@
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/* FfeUpdGainForce */
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#define FFE_UPDATE_GAIN_FORCE BIT(6)
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+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
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+/* TrFreeze */
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+#define TR_FREEZE_MASK GENMASK(11, 0)
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+
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
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/* SS: Steady-state, KP: Proportional Gain */
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/* SSTrKp100 */
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@@ -91,6 +95,11 @@
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/* SSTrKf1000Slv */
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#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
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+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
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+/* clear this bit if wanna select from AFE */
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+/* Regsigdet_sel_1000 */
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+#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
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+
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/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
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/* RegEEE_st2TrKf1000 */
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#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
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@@ -113,6 +122,10 @@
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/* RegEEE100Stg1_tar */
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#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
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+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
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+/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
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+#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
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+
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#define ANALOG_INTERNAL_OPERATION_MAX_US 20
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#define TXRESERVE_MIN 0
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#define TXRESERVE_MAX 7
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@@ -805,10 +818,7 @@ static void mt798x_phy_common_finetune(s
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FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
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FFE_UPDATE_GAIN_FORCE);
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- /* TrFreeze = 0 (mt7988 default) */
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- __phy_write(phydev, 0x11, 0x0);
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- __phy_write(phydev, 0x12, 0x0);
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- __phy_write(phydev, 0x10, 0x9686);
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+ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
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SS_TR_KP100_MASK | SS_TR_KF100_MASK |
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@@ -1009,10 +1019,8 @@ static void mt798x_phy_eee(struct phy_de
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MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
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phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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- /* Regsigdet_sel_1000 = 0 */
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- __phy_write(phydev, 0x11, 0xb);
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- __phy_write(phydev, 0x12, 0x0);
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- __phy_write(phydev, 0x10, 0x9690);
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+ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
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+ EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
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__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
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EEE1000_STAGE2_TR_KF_MASK,
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@@ -1036,10 +1044,8 @@ static void mt798x_phy_eee(struct phy_de
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FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
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0x10));
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- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
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- __phy_write(phydev, 0x11, 0x1463);
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- __phy_write(phydev, 0x12, 0x0);
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- __phy_write(phydev, 0x10, 0x96ca);
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+ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
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+ WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
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__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
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DFE_TAIL_EANBLE_VGA_TRHESH_1000,
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--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
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+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
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@@ -76,6 +76,13 @@ void __mtk_tr_set_bits(struct phy_device
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}
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EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
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+void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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+ u8 data_addr, u32 clr)
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+{
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+ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
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+}
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+EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
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+
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int mtk_phy_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
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--- a/drivers/net/phy/mediatek/mtk.h
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+++ b/drivers/net/phy/mediatek/mtk.h
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@@ -74,6 +74,8 @@ void mtk_tr_modify(struct phy_device *ph
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u8 data_addr, u32 mask, u32 set);
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void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 set);
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+void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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+ u8 data_addr, u32 clr);
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int mtk_phy_read_page(struct phy_device *phydev);
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int mtk_phy_write_page(struct phy_device *phydev, int page);
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