mirror of
https://github.com/coolsnowwolf/lede.git
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47 lines
1.9 KiB
Diff
47 lines
1.9 KiB
Diff
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From 5f707d3ff1b22c089253e39906b5edeeb5f10fdc Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Fri, 3 Apr 2020 15:31:59 +0530
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Subject: [PATCH] clk: qcom: ipq8074: SW workaround for UBI PLL lock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Some chip’s Huyara PLL is unable to lock in 5 us and
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generating UBI PLL lock error.
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WARNING: CPU: 1 PID: 625 at drivers/clk/qcom/clk-alpha-pll.c:114
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wait_for_pll+0xbc/0xe0()
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ubi32_pll_main failed to enable!
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CPU: 1 PID: 625 Comm: kmodloader Not tainted 4.4.60 #1
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Hardware name: Generic DT based system
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(unwind_backtrace) from [<8021b550>] (show_stack+0x10/0x14)
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(show_stack) from [<803f6b24>] (dump_stack+0x80/0xa0)
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(dump_stack) from [<80228ff0>] (warn_slowpath_common+0x84/0xb0)
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(warn_slowpath_common) from [<80229048>] (warn_slowpath_fmt+0x2c/0x3c)
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(warn_slowpath_fmt) from [<8054d53c>] (wait_for_pll+0xbc/0xe0)
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(wait_for_pll) from [<8054d6cc>] (clk_alpha_pll_enable+0xe0/0x128)
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(clk_alpha_pll_enable) from [<80547b68>] (clk_core_enable+0x68/0x98)
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(clk_core_enable) from [<80547b48>] (clk_core_enable+0x48/0x98)
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This is BUG in Huayra PLL HW for which SW workaround
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is to set bit 26 of TEST_CTL register.
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Change-Id: Ib5473f4011e3410515f382b2445bee2d66dd654a
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 3 +++
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1 file changed, 3 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -5068,6 +5068,9 @@ static int gcc_ipq8074_probe(struct plat
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/* Disable SW_COLLAPSE for USB1 GDSCR */
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regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
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+ /* SW Workaround for UBI Huayra PLL */
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+ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
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+
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clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
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clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
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&nss_crypto_pll_config);
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